I have downloaded and used this macromodel over the past several months. I have no reason to doubt its output when doing small-signal AC inputs that keep it in linear mode. However, the voltages at which it predicts that it will "rail" on either side of its DC output are simply wrong...sorry.... Upon investigation, I found this block in the model:
***Second Gain and Dominant Pole with Output Voltage Limiting
Gp1 51 201 101 0 2.663E-06
Rp1 201 51 Rideal 2.122E+08
Cp1 201 51 1.50E-12
Vlim1 97 206 3.45
Dlim1 201 206 dquiet
Vlim2 207 52 3.95
Dlim2 207 201 dquiet
Esupref1 97 98 51 0 1
Esupref2 52 51 51 0 1
When I saw the hard-coded values for the two Vlims, and drew up (and simulated) a schematic for this block, I immediately saw the reason. These values of 3.45 and 3.95 only make sense (reflect reality) when the chip is powered in some other way. We are powering with 10V and ground. To get behavior like we observe, I have to change both these values to something in the neighorhood of 1.85. In my view the macromodel needs to be (only) a bit more complicated in order to compute these hard-coded values flexibly from power-strategy inputs.
For designers, it would seem to me that knowing the railing levels could be important--in our case,for example, we need to know how much to divide this voltage range by, to stay within the safe range of an ADC chip we interface in a subsequent stage.
Does this make sense to you? If you have a more thorough macromodel somewhere, I'd encourage your publishing it!