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(ADV7181D) the status of output pins during PWRDWN

Question asked by donadona999s on Sep 28, 2016
Latest reply on Oct 14, 2016 by donadona999s

Hi !

 

I read this discussion.

[ADV7181D] the status of output pins during reset and after reset / the oscillator circuit (XTAL, XTAL1). 

But now I want to know the pin status when PWRDWN = L

Can you fill the spred sheet I attached ?

 

CategoryTypeNamesStatus after RESETB, with supplies stable and PWRDWNB highStatus during RESET active (RESETB Low), supplies stable and PWRDWNB highStatus after RESETB, with supplies stable and PWRDWNB low
Pixel Output PortOutputLLCToggleWill be driving either high or low 
Pixel Output PortOutputP10 to P19ToggleWill be driving either high or low 
Pixel Output PortOutputP0 to P9High-ZHigh-Z 
Sync OutputsOutputHS/CS, FIELD/DE, VSToggleDrive low 
Sync OutputsOutputSFL/SYNC_OUTDrive lowDrive low 
InterruptOutputINTBHigh-ZHigh-Z 
XTALInputXTALHigh-ZHigh-Z 
XTALOutputXTAL1ToggleToggle 
PLLOutputELPFDriving to VCO levelDriving to VCO level 
Analog InputsInputAIN1 to AIN10High-ZHigh-Z 
Analog InputsInputSOG, SOYDrive to a clamp levelDrive to a clamp level 
Analog InputsInputFB, HS_IN/CS_IN, VS_INHigh-ZHigh-Z 
Analog ReferenceInputCAPY1, CAPY2, CAPC2Drive to a reference levelHigh-Z 
Analog ReferenceOutputREFOUT, CMLDrive to a reference levelHigh-Z 
I2CInputALSB, SCLKHigh-ZHigh-Z 
I2CInput/OutputSDATAHigh-ZHigh-Z 
ResetInputRESETBHigh-ZHigh-Z 
Power downInputPWRDWNBHigh-ZHigh-Z 

 

Also at this discussion , 

LLC waveform of ADV7180 during reset. 

you said that "the digital outputs from the ADV7180 can become unstable this includes the LLC clock output."

Would the same thing will happen to ADV7181D?

If it would happen , would it happen to all digital output pins?

 

Best regards.

Kawa

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