AnsweredAssumed Answered

AD9361 GPIO

Question asked by lesley on Sep 27, 2016
Latest reply on Sep 29, 2016 by DragosB

Hi all,

      I have a question about the no-os driver code of fmcomms3.(the platform we use: fmcomms3+VC707)

      In the hdl, we want to use axi_gpio ip core to create sync_in pulse and resetb signal, so we connect gpio_sync pin with gpio_o[45] which is the 13rd bit of channel 2.

      However in the no-os driver code, the addresses in the gpio_data() and gpio_direction() functions are registers of channel 1.

 

 

      Should I change XGPIO_TRI_OFFSET and XGPIO_DATA_OFFSET to XGPIO_TRI2_OFFSET and XGPIO_DATA_OFFSET? And the GPIO_SYNC_PIN we define should be 13 or 45?

   admin JohannesHanalog-admin DragosB

Regards,

Lesley

Outcomes