PLL synthesizers that won't lock are one of the most common synthesizer problems we see. While modern PLL synthesizers can include a wide range of functions to optimize performance, at their core they have the same basic needs. These needs include: proper biasing, a spec compliant reference and RF signal for comparison when they meet at the phase frequency detector and a functional loop filter. This document isn't intended to address every PLL locking issue that exists on the ADF5355 as there can certainly be other factors. The primary purpose is to serve as a basic troubleshooting aid to help those in need logically troubleshoot the evaluation board (or their own layout) as a first course of action. Finally, it assumes that that the ADF5355SD1Z evaluation board or a layout and schematic that mimics the evaluation board is being used.