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[AD9361] Disabling PLL of the FMComms2 Receiver

Question asked by cmambatali on Sep 26, 2016
Latest reply on Sep 28, 2016 by cmambatali

Hello! I am Charleston Dale M. Ambatali, a lecturer from the Electrical and Electronics Engineering Institute from University of the Philippines - Diliman Campus.


I want to demonstrate the effect of the phase difference between the transmitter and receiver. I am using a Xilinx ZedBoard and an AD-FMCOMMS2-EBZ board. I have programmed the radio as such (based from the cyclic-sine example):


It sends a pure RF tone. The receiver DC correction is disabled. The block diagram of my setup is shown below:

I run the program twice and get two DIFFERENT results. I suspect that it is the effect of the PLL. If I could disable it, I may be able to demonstrate the effect of a non-coherent transmitter and receiver in communications. These are the results run in different times:

As you can observe, the setup behaves in a time-variant manner. I disabled the DC correction and the automatic gain control and I still have this problem. Is it the effect of the PLL or is it something else?