" SCL Clock Divider Register
CLKDIV = TWI SCL period / 10 MHz time reference
Serial clock frequencies can vary from 400 KHz to less than 20 KHz. The resolution of the clock generated
is 1/10 MHz or 100 ns. For example, for an SCL of 400 KHz (period = 1/400 KHz = 2500 ns) and an internal
time reference of 10 MHz (period = 100 ns):
CLKDIV = 2500 ns / 100 ns = 25
For an SCL with a 30% duty cycle, use TWI_CLKDIV.CLKLO = 17 and TWI_CLKDIV.CLKHI = 8. "
Above text i have taken from the ADSP-CM40X MIXED-SIGNAL CONTROL PROCESSOR WITH ARM CORTEX-M4 HARDWARE REFERENCE, page number 18-19. (ie. chapter 18, page number 19).
Can you please explain, how do we know TWI_CLKDIV.CLKLO and TWI_CLKDIV.CLKHI values before, to calculate duty cycle ?
How does the value of CLKDIV (25) is equal to 30% duty cycle and CLKLO=17 and CLKHI=8 ?
And to get 50% duty cycle, what is the value of CLKHI and CLKLO bits, and how do we calculate?
Thanks in advance.