AnsweredAssumed Answered

ADV7612 Vertical Sync Lock Failure

Question asked by graydean on Sep 23, 2016
Latest reply on Oct 5, 2016 by GuenterL

We have an HDMI board design that uses the ADV7612 non-HDCP part.  The front end of the design is largely based on the dual-ADV7612 sample design.  With a known good 720p input, and configuring the chip with the recommended settings, we get cable detect and PLL lock properly, but we cannot get the vertical sync filter lock.  With the same hdmi source, using the EVAL-ADV7612-7511P board, and the same recommended settings, the vertical sync filter locks without a problem.

 

We have attached a spreadsheet showing the register settings of every map in the Eval board versus our board.

 

On boot of the boards, we simply set the following registers:

98 f4 80
98 f5 7c
98 f8 4c
98 f9 64
98 fa 6c
98 fb 68
98 fd 44

recommended settings:
44 6c 00
68 9b 03
68 6f 08
68 85 1f
68 87 70
68 57 da
68 58 01
68 03 98
68 4c 40

set vid_std and prim_mode:
98 0 a
98 1 5
98 2 f2
98 3 42

power up chip:
98 c 42

hpa control:
68 6c a3

enable termination:
68 83 fc

 

Does anybody know what could possibly prevent the vertical lock when the PLL locks without a problem?  What in a circuit, compared to the EVAL circuit, can be causing this?  Since the same register settings are being made, and the same hdmi source is being used, it seems like it must be a circuit issue.

 

Thank you, in advance, for any help you can provide!

Outcomes