AnsweredAssumed Answered

ADF435x output two clock frequeny 2.2GHz/4.4GHz

Question asked by hoo on Sep 22, 2016
Latest reply on Sep 29, 2016 by rbrennan

ADF4351 OUT_A drive a ADC chip,while OUT_B drive a DAC chip,OUT_A enable divider and with value 2,OUT_B  is the fundamental VCO frequency,here is the situation:



set VCO to 4.4GHz,ADF4351 can not locked,output frequency is not 2.2GHz/4.4GHz;



lower VCO frequency to 3GHz, ADF4351 function well and locked,  output frequency is 1.5GHz/3GHz;


Disable OUT_A divider,set VCO to 4.4GHz, ADF4351 function well and locked,  output frequency is 4GHz/4GHz;


ADF4351 reference input is 20MHz XO, PDF is 10MHz(R=2),Loop filter bandwidth is 20KHz.

below is the schematic:


Change the design to below:


Problem remains,Test 1& Test 2 result is the same with Design 1


I can not understand why  ADF4351's output divider influence PLL locking??

I can not even understand why two dependent ADF4355's output influence each other??


I need two related clocks,2.2GHz/4.4GHz,with output divider enabled,VCO max frequency is 4GHz while ADF4351 locked,otherwise lock failed.


what else can i do?help me!!!