I am working on custom board using zynqsoc 7030 and ad9361 .(fmcomms3). I have included my custom logic (fm demodulator) in FPGA part in between ad9361 and adc pack.So my rx path is as follows.
ad9361 --> fm demodulator-->adc pack-->adc dma--zynq processor
I want to know some details..
1)I am using l_clk from ad9361 for my custom block. ADI IIO Scope is used for setting sample rate . I using the sample rate 1.536MSPS. And i got an observation that l_clk = 4times sample rate (6.144MSPS).So i have designed my module using this sample frequency(6.144MSPS). Is there anything wrong in doing like this?
input sampling rate 6.144MSPS and output is 96kHz.
2)From where ADI IIO Scope gets input?? I am asking this question because , when i modify the PL section as explained above.I am not getting any output.
Please help me.
Thanks in advance.