How is YUV 4:2:2 video input at 4K handled in the ADV7169,
and specifically what output interface modes are supported?
(e.g. pass through to 20 bit wide LVDS?)
Do you have one of our evaluation board for ADV7619?
As per data sheet reference, for video formats with pixel clocks higher than 170 MHz, the video signals received on the HDMI receiver are output directly to the pixel port output. To accommodate the higher bandwidth
required for these higher resolutions, the output on the pixel bus consists of two 24-bit buses running at up to 150 MHz: one bus contains the even pixels, and the other bus contains the odd pixels. When these two buses are combined, they allow the transfer of video data with pixel clocks up to 300 MHz. Please refer table 12 of the data sheet for pixel bus configuration. You can also refer the script file :03-02 YCbCr 422 In - 2x24-bit YCbCr 422 Out - For use up to 4k2k: which is available in ADV7619 design support files as reference for you.
Thanks for your response.
When you refer to even pixels and odd pixels do you consider
a pixel to be YCb on bus and the corresponding YCr on the other?
And, can you comment on any plans for a device that will support HDMI2.0 = 4KP60 (3840*2160 60P)?
Specifically, would this output interface be the same, just twice as fast, would you go
DDR on the same speed, or perhaps go LVDS, MIPI-CSI or something like that?
The HDMI 2.0 receiver has a 28 bit DDR LVDS output bus. Please contact your local FAE or sales rep for more information on these devices.
I’m just looking into parts for a reference design.
Could you provide a part number for the HDMI 2.0 receiver?
28 bit LVDS sounds like 2x 14 bit LVDS which is just right for me
(I need 20 bit LVDS for 10 bit pixel YCbCr 4:2:2 pixel components)
Sorry—I see you sent a link to the 9127A.
Regarding your odd pixel and even pixel question, you can refer UG-237 ADV7619 Reference manual Table 83 from ADV7619 Design Support files
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