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Output jitter without using internal PLL

Question asked by flai71 on Aug 17, 2011
Latest reply on Oct 19, 2011 by flai71

Hallo,

I have a problem with my DDS application getting output jitter if the internal PLL is not used.

Attached the schematic to see how the AD9958 is connected. I didn't put all pages to make it simple, even though I have three devices in the same board.

I have a programming setup that allows me to generate the desired output frequencies. Such a setup is below listed.

  

Chip select HIGH (default state)

 

Chip select LOW

Instruction byte = 0 (for CSR register)

CSR = 0x40 (0x40 for first channel or 0x80 for second channel)

Chip select HIGH

 

Chip select LOW

Instruction byte = 1 (for FR1 register)

FR1[23..16] = 0x97

FR1[15..8] = 0x00

FR1[7..0] = 0x00

Chip select HIGH

 

I/O update HIGH

I/O update LOW

 

Chip select LOW

Instruction byte = 2 (for FR2 register)

FR2[15..8] = 0x00

FR2[7..0] = 0x40

Chip select HIGH

 

I/O update HIGH

I/O update LOW

 

Chip select LOW

Instruction byte = 2 (for FR2 register)

FR2[15..8] = 0x00

FR2[7..0] = 0xC0

Chip select HIGH

 

I/O update HIGH

I/O update LOW

 

Chip select LOW

Instruction byte = 3 (for CFR register)

CFR[23..16] = 0x00

CFR[15..8] = 0x03

CFR[7..0] = 0x00

Chip select HIGH

 

I/O update HIGH

I/O update LOW

 

Chip select LOW

Instruction byte = 3 (for CFTW0 register)

CFTW0[31..24] = 0xDATA

CFTW0[23..16] = 0xDATA

CFTW0[15..8] = 0xDATA

CFTW0[7..0] = 0xDATA

Chip select HIGH

 

I/O update HIGH

I/O update LOW

  

I admit no use of the Master Reset after power-up; but the device work properly.

 

With such a programming the DDS works internally at 500MHz; refclk 100MHz multiplied 5 times.

On pin SYNC_OUT I get 125MHz. Problem is that VoH is 1,5V only and the buffer 49FCT3805 is out of spec on both ViHmin and Maxfreq.

I tried to reduce PLL freq to 400MHz writing 0x93 in the FR1 register most significant byte. That works but still the SYNC_OUT VoH level is low, around 1,7V.

I didn't understand why it is so low. Either I didn't find on the datasheet a frequency limit for that pin, so that I assume it can run up to Max PLL freq divided time 4.

Forced to get the right VoH level on the SYNC_OUT pin I tried to don't use the PLL writing 0x00 in the FR1 register most significant byte.

The SYNC_OUT pin has a excellent 25MHz square wave with 25% dutycycle.

Counterwise the DDS outputs has a huge jitter that makes it unusable.

Could you please advise what I am doing wrong in my programming or connection? Or other idea on how to solve the SYNC_OUT level problem?

 

Thanks

 

Regards

 

Flavio

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