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AD9361 problem with clk_out

Question asked by vbif on Sep 22, 2016
Latest reply on Sep 22, 2016 by vbif

Try to configure output clock from no-os driver, and get strange result for ADC_CLK_DIV_2 and ADC_CLK_DIV_3

 

enum ad9361_clkout {
CLKOUT_DISABLE,
BUFFERED_XTALN_DCXO,
ADC_CLK_DIV_2, -> work like div1
ADC_CLK_DIV_3-> work like div2
ADC_CLK_DIV_4, -> work like div4
ADC_CLK_DIV_8, -> work like div8
ADC_CLK_DIV_16,
};

 

Is it normal? or I have an error in my measurement?

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