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Clarifications needed on ADV7180

Question asked by Santosh on Aug 17, 2011
Latest reply on Aug 18, 2011 by DaveD

Hello All,


I have few questions regarding ADV7180 settings - Please help me to understand  the below questions.

  1. Video Specifications – LOCK TIME SPECIFICATIONS - Page number 7
    1. Horizontal Lock Range – The data sheet says ADV7180 has -5 to +5 %. Is it that, even if there are -5 to +5% of pixels less/more on each line of video input(HSYNC), ADV7180 can still lock to the HYNC? I would like to understand more on this. And let us say that there is -5 to +5 % change in the video input to ADV7180, then what will be the output of ADV7180? Will it be always 720 pixels or according to the input?
    2. Vertical Lock Range – The data sheet shows 40 to 70 Hz. Please explain this also.
    3. Vertical Lock Time – The data sheet says that, 2 fields are needed to lock to the video. If let us say we get a VSYNC and followed by very less HSYNCS(let us say 10) and again followed by a VSYNC. That is the second VSYNC has come before completing all the HSYNCS of a previous field(short filed),  In this case what will be the output from the ADV7180?
  2. Register 0x51 – Lock Count – CIL[2:0] - count into lock determines the number of lines the system must remain in lock before showing a locked status
    1. I have set the value for CIL[2:0] to 7 . That is 100,000 lines of video. What I understand from this is that, only after 100,000 valid lines of video are detected, the lock status is set in ADV7180. However with our experiments we are seeing that it is not happening. If we have NTSC video, it should have taken at least 5 seconds to get it locked. But we are seeing that the lock interrupt comes in less than a second.  Can you please explain this behavior? We have enabled line to line evaluation in "SRLS, Select Raw Lock Signal, Address 0x51[6]" register.