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ADCMP572 LE logic levels

Question asked by timothy.starr on Sep 21, 2016
Latest reply on Feb 21, 2017 by bchwang


The question refers to the ADCMP572 and the connection to the Latch Enable inputs.

The specification states that the LE and ~LE need to be differential with a min of 0.2V, nominal 0.4V and max of 0.5V


The specification has a picture of the latch enable, but is missing the Tpl spec that go with the picture.


At what differential voltage does the latch disable (min typ max)?

Does the latch have any hysteresis?

Or is the 0.2V actually the hysteresis of the Latch Enable?


The spec states that if you want to disable the latch  tie ~LE low with a 750 Ohm resistor (if using 3.3V for Vcco). This brings ~LE 0.206V below LE.  If I want to latch the output, I now bring LE down. Does it latch when I bring LE down by 0.006V, or do I need 0.206V, or do I need 0.412V?

Same question applies when I let LE go back up.

If the absolute difference between LE and ~LE is less than 0.2V, is the output latched or not    or is this an undetermined state?


Also is there a valid spice model of ADCMP572?

-Tim Starr on behalf of JM@ES