We have used the AD9854 DDS chip for many years very successfully, but now wish to upgrade to (possibly) the AD9910 to gain advantage from the better phase noise and spurious specs.
The AD9854 is used as follows:
Single Tone mode
System clock 300MHz
FTW consists of 24 bits loaded in three 8-bit segments using an external 60MHz clock (synchronised with the 300MHz), and loaded via I/O Update using a 20MHz clock, again synchronised. The remaining 24 bits of the tuning word are all permanently set to 0.
The output consists of a series of pulses (typical pulse length from 1us to 1ms) with no signal in the dead time between pulses (typically greater than 100us). These pulses are highly non-linear in frequency, but constant in amplitude.
At the end of each pulse, the phase accumulator is reset thus ensuring zero phase and frequency at the start of each pulse.
If the AD9910 is suitable, I would use a system clock frequency of 900MHz and change the FTW to a 32 bit word, loaded as two 16 bit words.
Obviously the serial data link is far too slow, so the parallel port will need to be used.
As an analogue/power engineer, I am somewhat confused by some of the terms used in the data sheet.
As I read it, I think that the FTW word is loaded into some register (?) in two 16 bit words, being steered to the correct destination using the FM gain (how?), the final 32 bit word then loaded into the DDS core using the I/O Update (using the present 20MHz clock).
Assuming this is correct, the bit which is really confusing me is the statement that the "16 bit data word serves as an offset to the 32 bit frequency tuning word in the FTW register".
I should add that the parallel port will not be used for any other function.
Can you confirm that the AD9910 is suitable for me to use in the same fashion as the AD9854 is currently used, and could you please translate the FTW word loading procedure into English that an analogue engineer can understand?