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AD7091R CS\ and CONVST\ Timing

Question asked by dec on Sep 20, 2016
Latest reply on Sep 21, 2016 by Gnib

I am considering use of the AD7091R.  I would like to trigger the generation of the short CONVST\ pulse using the falling edge of the chip select CS\.  So, from the AD7091R perspective, this means that the chip select would start just before the falling edge of CONVST\.  The datasheet doesn't discuss any timing restrictions/specs regarding falling edge of chip select relative to falling edge of CONVST\.  Of course the busy bit would be a part of the transfer.  This is ok.  Of course the clock would be delayed until well after the EOC was complete.


I marked up the datasheet timing diagram and pasted below...




Can someone confirm that it is safe to assert the CS\ signal before asserting CONVST\?