I'm trying to interface the AD9910 eval board to an FPGA board, and use the max communication rates of the DDS serial port (70 mbps according to AD9910 datasheet). The FPGA board outputs can be configured as LVDS or single-ended LVCMOS. I'm using a 20cm length of ribbon cable to connect the two.
I naively thought that the cable wouldn't distort the SCLK and SDIO signals too much, so I tried to run the serial port with LVCMOS. The SCLK rise/fall times are ~10 ns with ringing, which is way above the 2ns maximum in the datasheet, and the 9910 understandably doesn't respond. The 9910 works fine under PC control. I'm trying to read CFR3; i.e. I'm sending over 0x82 in the instruction byte, then sending over 32 SCLK cycles while monitoring the SDIO pin for signs of life. For now I keep MASTER_RESET high except during serial comms.
I'm currently thinking I should use the outputs in LVDS mode and dead-bug an LVDS-to-LVCMOS receiver close to the board headers. This is not ideal, and I was wondering if anyone could give me some thoughts on better/easier techniques to use?
Best regards, and thanks in advance!