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AD9371 JESD204b bit mapping

Question asked by Mike4fpgas on Sep 16, 2016
Latest reply on Sep 21, 2016 by rejeesh

I am looking for the bit mapping between the I/Q samples and the JESD204B interface (Xilinx calls it the transport layer) for the 2 converter-4 lane mode and also the 2 converter-2 lane mode. Also, I see references to AD9371-UG-992, which may contain these answers, but I cannot find it on the AD website.

Here is an example of what I am looking for:

adc0_sample0 = {rx_tdata[7:0], rx_tdata[39:32]}; // ADC0 sample N

adc0_sample1 = {rx_tdata[15:8], rx_tdata[47:40]}; // ADC0 sample N+1

adc0_sample2 = {rx_tdata[23:16], rx_tdata[55:48]}; // ADC0 sample N+2

adc0_sample3 = {rx_tdata[31:24], rx_tdata[63:56]}; // ADC0 sample N+3

adc1_sample0 = {rx_tdata[71:64], rx_tdata[103:96]}; // ADC0 sample N

adc1_sample1 = {rx_tdata[79:72], rx_tdata[111:104]}; // ADC0 sample N+1

adc1_sample2 = {rx_tdata[87:80], rx_tdata[119:112]}; // ADC0 sample N+2

adc1_sample3 = {rx_tdata[95:88], rx_tdata[127:120]}; // ADC0 sample N+3

 

Thank you.

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