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AD9523-1: availability of the clock on the PLL1_OUT at the power-up

Question asked by luca.banchi on Sep 16, 2016
Latest reply on Sep 26, 2016 by luca.banchi

Dear support,

 In my design I will adopt the AD9523-1 as clock generator and clock buffer. In particular I will bypass the PLL1 connecting my reference oscillator (REF) directly on the OSC_IN input of the AD9523-1.

I would like to know if, at the very power-up of the AD9523-1, a replica of the REF clock is available on the PLL1_OUT, even if the device is still not programmed (only powered-up).

I ask this question because I am trying to figure out if, at the power up of the board, there is an available clock to be provided to an FPGA on the same board.

 

Thank you for your reply

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