I encounter problems dealing with the Fast Lock mode of the ADF4158. As in my own circuit the fast lock mode wouldn`t work, I tried it out with the evaluation board of the chip. Here I have the same problem. I use the green evaluation board and the corresponding evaluation software. I equipped the R1a and the R2a with 820 Ohm and 1kOhm (see loopfilter.png). "ADISIMFL.png" and "ADISIMnoFL.png" show the simulation of my settings with and without the Fast Lock mode. "PLLSoftware.png" and "PLLSoftware2.png" show the Register settings I`ve sent to the board for the test without the fast lock mode. The result can be seen in Measurement_without_fastlock.pdf. This was measured with the "Rhode&Schwarz Signal&Spectrum Analyzer". I switched the board off and on and triggered with the LoadEnable pin. As the last register (R0) was written, the measurement began.
I did the same for the test with fast lock mode. Difference was, that I just changed the CLK Div Mode to"Fast Lock Divider".
In "Measurement_with_fastlock.pdf" you can find the result.
As you can see, the fastlock did not work correctly. I`ve tried many different settings in the Pll sofware, but that didn´t work out. Do you have any idea, why it doesn´t work?