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AD9371 Datasheet clarification

Question asked by Belenie on Sep 14, 2016
Latest reply on Oct 19, 2016 by Vinod
  1. a) Datasheet of AD9371 page 50 it has Rx EVM vs input power on the main receiver. Do they also have SNR vs. input power?(can you confirm this is 64QAM modulation)?
  2. b) Datasheet of AD9371 page 58 calls out the JESD204B lane count for 2Tx and 2RX requires total of 5 lanes(20MHz Tx and Rx), does it include ORx and Sniffer Rx path?

In terms of connecting those lanes/pins from 9371 to FPGA can I say one lane requires a pair of high speed IO pins(2 pins)?

 

Thanks

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