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AD9361 TDD burst pulses before data

Question asked by jyripoldre on Sep 15, 2016
Latest reply on Sep 16, 2016 by sripad
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Both Rx1 and Rx2 channels have ~2 us bursts before data start following transfer from ALERT to RX state that cause AGC to converge to incorrect level. Platform is FMCOMMS2 board on Xilinx AC701 development platform running two 56Mhz burst modems targeted for XPIC solution. Burst length is configurable for different forward and return channel bandwidths, currently 4 msec in each direction. Programming is done through NO-OS API. ENSM is controlled with txnrx/enable from FPGA. Two boards are connected with Tx attenuation set to -20 dB.

Link works with manual gain (32 dB) in FDD mode but will remain at low gain when using Fast AGC and TDD. 

These peaks are there even if rx inputs are grounded with SMA terminators and present also for  FDD independent mode.  The only mode where burst starts clean is FDD mode without external ENSM pin control.

 

In attached diagram one step is 16 NS, burst data wil start after 50 usec.

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