i evaluate the ad9653 with hsc-adc-evalcz fpga board + eval ad9653 board.
when i using visual analog , the sample result is right, but when i use the ad9653-fifo5-fpga source code firmware with xilinx chipscope , the result is wrong.
The output timing adjustment I am referring to is in the ADC, not in the FPGA code. By changing values in AD9653 Register 0x16 Bits[3:0] you should see the waveform change if Data-to-DCO timing is affecting capture.
Are you using SPIController software ( http://www.analog.com/en/design-center/interactive-design-tools/spicontroller.html ) to configure the AD9653?
Thank you for your interest in AD9653.
One thing to try is to adjust the timing relationship between DCO and Data, using Register 0x16 Bits[3:0]. Please try different settings and see if this changes the waveform you see in ChipScope.
What FPGA board are you running ChipScope with?
thank you Dougl for your reply.
i use the adi recommended fpga board hsc-adc-evalcz and the firmware which was download from the ftp of the anlog.
i will try your advice. But i am confused why the firmware and eval fpga board which came from ADI could not work correctly
It could be that the FPGA program (.bin) released with VisualAnalog is a different version than the source code.
As an experiment you could try the .bin file provided with the source code. Please keep in mind that the source code is provided as a benefit to you so you can see how the outputs are captured. The source code is provided free, as-is and is not guaranteed.
Please try the output timing adjustments and see if that helps.
i try to change the phase shift many times in the dcm_top module of the project. But nothing changed.
Could you supply the fpga source code of the visualAnalog bin file or give some advice about the proper phase shift？
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