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ADAU1761 TDM8 Master mode problems

Question asked by pbthesp on Sep 14, 2016
Latest reply on Sep 21, 2016 by pbthesp

We have set up an ADAU1761 as followsi

TDM8 mode.

bus master.

LRCLK is set to pulse

BCLK cycles to 256

BCLK as falling edge

Delay of 1bit


No data comes out when LRCLK is set to rising edge.

Data comes out when LRCLK is set to falling edge.

if LRCLK is set at 50% it will work on rising or falling edge


This has been checked on an eval board through Sigma Studio and on our prototypes by setting register 0x4015.

This seems very strange as TDM requires rising edge polarity on LRCLK as pulse.


If we set delay to 0 bits and LRCLK falling edge the data looks to be changing on the rising edge of LRCLK