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Questions about AD9371 RF settling time

Question asked by JunHu on Sep 14, 2016
Latest reply on Sep 19, 2016 by sripad

hello all,

 

Recently, we are trying to use AD9371 to build a 100MHz BW self-defined TDD based system, obviously it will introduce UL/DL or DL/UL transition. To make sure the data quality, we will try to reserve certain GAP for transition

 

But by looking at the data sheet or user guide, I did not find certain descriptions about the RF settling time spec for UL/DL.

(maybe I missed it during reading...)

 

Can anyone kindly point out the related descriptions in data sheet or user guide ??

 

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BTW: during searching the potential settling time information,

I found in user guide UG-992,  'system control --> control of signal chains (Tx/Rx)', (page 285), 

two kinds of control signals are mentioned, which are TX/RX_enable and TX/RX_enable_ack,

the latency b/w TX/RX_enable and TX/RX_enable_ack is 2us in max.

 

I am just wondering about the following items:

a). What is the exact meaning and purpose of TX/RX_ENABLE_ACK, from the view of BBP ??

b). Are TX/RX_ENABLE_ACK  just represent HW control delay (or control timing resolution) after TX/RX_enable is triggered or they have already included the RF settling time ??

 

Really appreciated for the help!

 

BRs,

Jun Hu

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