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Rise / Fall Times on SDO with Shared SPI Bus HMC PLLs

Question asked by youngguns21 on Sep 9, 2016
Latest reply on Sep 16, 2016 by DonY

Has anyone seen poor rise / fall times on the SDO line when using the HMC PLL/VCOs over a shared SPI bus?

 

I'm seeing rise/fall times of ~100ns when the PLLs are on a shared bus, and there's no external capacitors on the bus. Individually, each PLL is ~15ns rise/fall. 

 

Also, this is not a problem on the SCK or SDI lines, just the SDO line. 

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