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[AD-FMCADC4-EBZ][ZC706] What do I need to generate bitstream from HDL ?

Question asked by Rubisoft on Sep 9, 2016
Latest reply on Sep 16, 2016 by rejeesh

Hello everyone,


I am working on a Xilinx Zynq ZC706 board and a AD-FMCADC4-EBZ board. My ZC706 was delivered with a Vivado 2015.4 license. I added the Vivado 2015.4 Update 2 too. I'm working on a dual boot PC with:

  •  W10 x64 with a full CygWin installation 
  •  Ubuntu x64 16.04.1

On my ZC706 board I got two SD card available with two different Linux setup from AD:

1) The default Zynq Linux (Linaro 12.11) image given here :

      Which contains a full GUI environment for testing the FMCADC4 board (ADI IIO Oscilloscope etc...)

2) The same default Zynq Linux image but I manually changed the RootFS to get a less heavy OS. I used the Linaro 12.11   developer RootFS which can be found here:

And installed using those commands under Ubuntu :

//To format the SD RootFS partition

$sudo rm -r -f /media/<username>/rootfs/*             


// Writing the new RootFS in the same formated SD partition

$ sudo tar --strip-components=3 -C /media/<username>/rootfs/ -xzpf linaro-precise-developer-20121124-513.tar.gz binary/boot/filesystem.dir        

Since my Linaro setup is done and functional and my final goal is to be able to flash the FPGA from Linux using the $ cat command,  I understood after reading a few threads:

Solved: Zynq: Loading bitfile into FPGA from Linux (xdevcf... - Community Forums 

That all I needed to do next was find out how to generate the .bit file which is used by $cat.
For this, I decided to start from the AD HDL Design which can be found here:

GitHub - analogdevicesinc/hdl: HDL libraries and projects 

And I followed this building guide:

Building HDL [Analog Devices Wiki] 
So using a terminal I launched the $ make all command in the /projects/fmcadc4/ directory which crashed when trying to generate the bitsream:

$ make all
make -C zc706 all


vivado -mode batch -source system_project.tcl >> fmcadc4_zc706_vivado.log 2>&1
make[1]: *** [Makefile:76: fmcadc4_zc706.sdk/system_top.hdf] Error 1
make[1]: Leaving directory '/cygdrive/d/Systeme/Dossiers_Systeme/Bureau/a/a/projects/fmcadc4/zc706'
make: [Makefile:10: all] Error 2 (ignored)

Then I went to the fmcadc4_zc706_vivado.log file and found this error:

Finished Running Vector-less Activity Propagation
report_power: Time (s): cpu = 00:00:19 ; elapsed = 00:00:13 . Memory (MB): peak = 2473.902 ; gain = 0.000
Attempting to get a license for feature 'Implementation' and/or device 'xc7z045'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z045'
INFO: [Common 17-83] Releasing license: Implementation
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
i_system_wrapper/system_i/axi_ad9680_jesd/inst/i_system_axi_ad9680_jesd_0 (jesd204_v6_2_1_top)

So hear is my question: what does generates this error message? What license do we need to build the AD HDL designs? Is the license given with my ZC706 adequate for this?


If needed I attached to this post the full $make all output and the .log file. Also attached, a screen capture of the Xilinx License Manager.

I just want to be sure this error is due to a licensing problem before buying any additional license.

If anyone has an idea? Feel free to correct me if i made mistakes in my understanding of the system.


Thank you for your help !


Antony L