AnthonyTung

ADF4158 - Frequency drift with PLL locked

Discussion created by AnthonyTung on Sep 9, 2016
Latest reply on Sep 18, 2016 by AnthonyTung

Hi ADI members,

 

We use the below and attachment component to implement the PLL architecture.
(Our design is the follow attachment ADI UG-123.pdf reference design)

 

Synthesizer: ADI ADF4158

VCO: Zcomm V940ME03-LF__

 

 

Question:

Now, we found the frequency drift when PLL locked.
And drift range is about 200Hz variation.

Could you have any solve idea about the question? Or the issue impacted by what factor?

 

 

Thanks,

Anthony

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