Hi ADI members,
We use the below and attachment component to implement the PLL architecture.
(Our design is the follow attachment ADI UG-123.pdf reference design)
Synthesizer: ADI ADF4158
VCO: Zcomm V940ME03-LF__
Now, we found the frequency drift when PLL locked.
And drift range is about 200Hz variation.
Could you have any solve idea about the question? Or the issue impacted by what factor?