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How to test TX to RX loop-back data path using SPI Register 0x3F5—BIST Config2, D0—Data Port Loop Test Enable?

Question asked by leonid.k on Sep 8, 2016
Latest reply on Sep 9, 2016 by Vinod

I build a JTAG test program for design with AD9361 and attempting to test TX - RX buses using loop-back mode:

SPI Register 0x3F5—BIST Config2, 

D0—Data Port Loop Test Enable
When set, this bit loops Tx I/O data back onto the Rx I/O port.
If in half duplex mode, also set D7.

After this bit written high, TX bus toggling does not cause to RX bus changes.

What a register write sequence should be implemented for this purpose?