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Question asked by liuheng on Sep 8, 2016
Latest reply on Sep 8, 2016 by JeyasudhaMuthuPerumal

Now,we encountered such a problem: our 1080 p/50 output will cost in some scenarios jitter and screen,
 ADV7842 some regisiters  following:

{0x40 0x3 0x80
0x40 0x0  0x1e
0x40 0 x1 0x15
0x40 0x2  0xf0
: the output format for 16 - BIT ITU - 656 SDRS MODE
Schematic diagram output on the corresponding pin is:Y {P23 - P16}, CBCR {P11 - P4}, 16 bits wide, whether can support 1080 p / 50 hz output?
Whether also need to configure the other registers to implement?