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AD9371 VDD_IF power domain related IO pin question

Question asked by fredCY on Sep 7, 2016
Latest reply on Sep 15, 2016 by sripad

From AD9371 datasheet, the description of VDD_IF is CMOS/LVDS Interface Supply.

 

Question1: How many digital pins are referred to the VDD_IF power domain? The following list is my understanding. Is there any mistake or missing pins? 

CMOS: (1) GPIO_0 to GPIO_18

             (2) RESET

             (3) GP_INTERRUPT

             (4) SDIO, SDO, SCLK, CSB

             (5) RX1_ENABLE, RX2_ENABLE, TX1_ENABLE, TX2_ENABLE

             (6) TEST

 LVDS:  (1) SYNCINB0-, SYNCINB0+, SYNCINB1-, SYNCINB1+, SYNCOUTB0+, SYNCOUTB0-

             (2) SYSREF_IN+, SYSREF_IN- 

 

Question2: CMOS and LVDS pins input/output level. 

CMOS: Refer to VDD_IF. For example of CMOS input pins, if VDD_IF=1.8volts, then VIH should be > 1.8volts*0.8=1.44Volts and VIL should be <1.8volts*0.2=0.36volts

LVDS: Although referring to VDD_IF, the LVDS input and output pins level or threshold are fixed as the following table(a) whether 2.5volts or 1.8volts are used for VDD_IF

 

Is the understanding right?

 

table(a) from AD9371 datasheet

 

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