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ADV7180 IC register configuration and free run mode selection

Question asked by Bhavyak on Sep 7, 2016
Latest reply on Mar 21, 2017 by Rob.Analog



I am using a ADV7180 IC to output a 16bit YCbCr 4:2:2 video format by using a PAL camera input. I am not using the HS,VS/field outputs from the decoder as I am using it in embedded sync mode. I have configured the following set of registers in the below mentioned sequence


42 0F 80 ; reset register
42 00 00 ; INSEL = CVBS in on AIn 1
42 03 09 ; 16-bit at LLC 4:2:2
42 14 30 ; Reset Clamping Circuitry
42 04 57 ; Enable SFL
42 17 41 ; select SH1
42 31 02 ; Clears NEWAV_MODE, SAV/EAV to suit ADV video encoders
42 3D A2 ; MWE Enable Manual Window, Colour Kill Threshold to 2
42 3E 6A ; BLM optimisation
42 3F A0 ; BGB
42 0E 80 ; ADI Required Write
42 55 81 ; ADI Required Write
42 0E 00 ; ADI Required Write
42 52 0D ; ADI Required Writes [ADV7180 writes finished]
42 8F 50 ; 13.5 MHz clock configuration for 16 bit interface


The output from decoder is converted to RGB format in FPGA and sent to ADV7123 encoder IC and then sent on AD725 IC to get PAL composite output. The output contains line noise as in attached snapshots. Is there any decoder settings to be modified to improve the video quality.

Also we are not able to output the ADV7180 in free run mode by writing to following registers as in ADV7180_RSD.pdf

42 0C 37 Force Free-Run mode

42 00 XX Force Video Standard1

42 0D YY Set Color Output2 

The display goes blank for any color value set. The status register 13h reads 0xFD but there is no display.
 So we are not able to isolate if the noise is due to the ADV7180 video decoder or due to the AD725 encoder side.