The SYNC Controller Initialization Description (Rev. C Datasheet Page 38) and the Recommended SPI Initialization with SYNC Controller Enabled (Rev C. Datasheet Page 48) both instruct to write 0x50 to register 0x10 to enable the slave sync controller. However, the Data Receiver Controller Configuration Register table (Rev C. Datasheet Page 24) says "Enable for master only" on bit 6 (SYNC_LOOP_ON), which would indicate a value of 0x10 is needed instead of 0x50. In steps 24-26 of the Recommended SPI Initialization with SYNC Controller Enabled, s = 5 would also need to be s = 1 to indicate that this bit should not be set.
The "Enable for master only" is inaccurate. Information contradicts itself. Which is correct?