I have a question about the Tx, Rx PLL CP calibration.
We are working in 3.XGHz frequency band.
1. According to the AD9361_Register_Map_Reference_Manual_UG-671 on page 60 the default value of register 0x23D and 0x27D should be 0x80 but D7 must be "0" so in that case how it is possible that the default value is 0x80 ?
2. What should be the value of these register after Reset ?
3. In order to activate the Tx, Rx PLL CP calibration we change the value of 0x23D and 0x27D to 0x04.
We noticed that in some AD9361 chips if we change the value of registers 0x23D and 0x27D to 0x00 after 0x244 = "1" and 0x284 = "1" (successful CP calibration) the SSB phase noise of the Tx frequency become unstable when we work with a frequency that has fractional value > 0.
Why is that ? What is causing the phase noise to become unstable when the fractional value > 0 ?
4. Can we keep registers 0x23D and 0x27D at 0x04 after the CP calibration is over ?
If we do so it solve the problem at question number 3.