We are studying a way to add user logic to the fmcadc2 reference design on a ZC706 board, but we are not sure on how to proceed. Specifically, as we have already posted in this forum, we intend to insert our logic between modules axi_ad9625_core and axi_ad9625_fifo. We have two questions:
- what is the timing of the input ports on the axi_ad9625_fifo module?
- is there any document that describes these modules?
- is the source code for these modules available?
Thanks to your instructions, we have already got to the point where we can compile the original reference design and load it into the FPGA usind the SD card. We are counting on you now to advance to the next step.