We are in the process of bringing up AD9467 eval board on XILINX Zynq7020 platform, using the Zedboard reference design for that purpose.
Instead of the DMAC provided in reference design, we are directly routing the data output of the 'axi_ad9467' block to a XILINX ASYNC FIFO and in turn to our internal DSP IPs. We are using the driver software APIs and executing them all the way till ADC Setup for Data Acquisition (skipping the last 'adc_test' step since that test uses the DMAC). We are also able to read back the registers of the AD9467 to check for programmed values, the contents looks right.
However, we are seeing a square waveform on the 'axi_ad9467' output data-bus switching between ~32K and 0, even when no Analog input is connected. Upon connecting an external analog source, this waveform seems to change a bit , but we are not getting the expected waveform. It looks as if the AD9467 is in some kind of internal loop back mode capturing a square waveform.
Could you please provide some insights into this setup issue, so that we can capture the ADC samples directly from the axi_ad9467 block. We do not have any documentation on the AXI_AD9467 registers, any help on this IP is greatly appreciated.
Thanks and regards