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AD9910: sycn_clk shows 'pulsing' master clock

Question asked by dlgochna on Aug 31, 2016
Latest reply on Sep 9, 2016 by JLKeip

As I read out the sync_clk on a scope, I see the expected frequency (250 MHz) within an envelope of a train of pulses (roughly 4 Mhz, with a duty cycle around 75%). I checked the power lines and several digital input pins separate from the board, and there is no noise at 4 MHz. (There is noise at this frequency when they are all connected to the board, but I suspect that may just be back talk from something on the eval board.)


I discovered this problem after I noticed the RF output was also exhibiting an envelope of a train of pulses at about 4 MHz. I have not been able to find a solution, however, and so I am hoping someone else may have an idea for why my board might be doing this.