I need to output 12 synchronized signals from 3 AD9959's. I am able to sync the sync_clocks via the automatic sync function, using the master slave topology and the set propagation delay. The problem I have is that I am unable to sync the actual output signals from the DDS's. After each initialization there is different phase difference between the IC's. The IO_update signals are synchronized on the FPGA with the individual sync-clocks (double buffered flip-flop). After an initialization the phase offset stays as is when I updated the phase register. I.E. I can set a phase correctly and also return to original phase after reset. But if I change the frequency, and come back to the original frequency , then I have a new phase offset........Randomly the phase offset is synced the same value after initialization. My question is the following: Am i missing something? I can read register FR2, and bit 5 stays low.....I.E. synced....I can also see on the FPGA that the sync-clocks are synced, but I have random behavior on the signal outputs after each reset. Do I need to sync the Reset siganl on the FPGA's? Also interesting is that the random phase normally has 4 states.......Any ideas?
Ref clk: 500 MHz from AD9510 with even-lengthed tracks.