I've been noticing there are slight frequency errors when trying to set the ADC sample clock to 61.44 MHz. This seems to be a common frequency setting from the examples I've seen. I'm trying to set the BBPLL to 983.04 MHz with an external reference clock of 10 MHz. The ref clock gets multiplied by 2x, and going through the equations for the BBPLL manually I get:

983.04 MHz = 20 MHz * (Nint + Nfrac/2088960)

This works out to Nint = 49, and Nfrac of 317521.92. Since Nfrac isn't an integer, it gets rounded off in the driver and BBPLL is slightly off. This is also true using the built-in 40 MHz reference clock on the FMCOMMS4.

Am I missing something here? I keep seeing these numbers (983.04 MHz, 245.76 MHz, 122.88 MHz, 61.44 MHz) in examples and documentation. What is special about these values, especially when you could hit 61.25 MHz with no frequency error given a ref clock that is a multiple of 10 MHz?

Hi,

983.04 MHz, 245.76 MHz, 122.88 MHz, 61.44 MHz these are common frequencies in the Communications and Infrastructure market. The baseband rates for e.g. LTE are derived from such a clock.

The max frequency error of the fractional baseband PLL can be expressed as.

ferr = Nfrac/2088960 * fref using Nfrac=1.

so for your 10MHz reference and the clock doubler - the max error is around 9Hz.

For your 61.44 case the actual error is 0.8Hz which is totally negligible given the frequency stability of your XO.

-Michael