AnsweredAssumed Answered

Question about ADAS3023 Timing Sequence [Urgent]

Question asked by Eric-Wang on Aug 29, 2016
Latest reply on Aug 29, 2016 by Eric-Wang

When I was trying ADAS3023 with FPGA, I can't get correct conversion result. I detect those signals with signal tap on FPGA, I find the timing sequence is different with that in datasheet.

Channal Transmission Sequence Question

in the picture above, I give 1 volt to IN0, but receive F49Fh on CH6 through SDO signal as shown above. My input range is 20.48V(by default). My cfg register is FFFFh, so the input result F49Fh can't stand for 1V. I wonder why.

Meanwhile, I find busy signal is different with that in datasheet. See picture below.

BUSY signal timing sequence inconsistent with datasheet

BUSY signal can't remain low after its falling edge, but in datasheet it is low after its falling edge.

As far as I'm concerned, I think the procedure of conversion and transmission is as below:

1. Rising edge of CNV trigger conversion(n).

2. Falling edge of BUSY shows the end of conversion(n).

3. Then you send low CS signal and SCK signal simultaneously to AD chip.

4. At first 16 falling edge of SCK, you transmit CFG regerster value to chip from MSB to LSB(eg. FFFFh)

5. Every rising edge of SCK, you receive a bit on SDO from CH0 to CH7 and MSB to LSB successively without interval or dummy bit.

 

Am I right about timing sequence?

 

By the way, I want to ask why there is periodic pulse on SDO when I give 0 volt to every channal. Shown as below.

you can see there is periodic pulses, so the value I receive from SDO is 0001h rather than 0000h. what's wrong with this?

Outcomes