We are trying to expand the AD9361 reference design (fmcomms5) to 6 AD9361 interfaces. Currently our hardware does not have one AD9361 entirely mapped to one bank of FPGA(Virtex7) i.e multiple AD9361 data ports are connected to one bank. We understand that iodelay_group works only if you have each AD9361 attached entirely to separate banks of FPGA. We are currently getting placement errors of having multiple iodelay_group in a single bank. Can we use iodelayctrl for all ports of AD9361 and remove iodelay_group entirely? Would it affect the performance or validity of the design?