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ADF7242: TX_EN isn't go to logical '0' at some length of data packet

Question asked by picovolt on Aug 27, 2016
Latest reply on Sep 2, 2016 by SteveH

Hello, dear Colleagues!

I have some troubles with data transmitting on ADF7242 chip.

Used configuration: GFSK, 2000 Mbit/s, packet mode.

After Inititialization (see below) I am writing data in PacketRAM, after that I start transmitting by means of issue RC_TX command. Simultaneously I monitor the logic level on TX_EN pin: if it is “High” – transmitting is in the progress, “Low” – transmitting is ended.

It has been observed that If I am trying to send 138 data bytes in packet – all is OK, all data are transmitting correct: TX_EN pin stays “High” during transmit mode, after that It goes to “Low”. Received data are correct.

However, if I write in the PacketRAM 140 data bytes and issue RC_TX, TX_EN pin goes “High” and never goes to “Low”.  As I am starting to write new packet of data in the PacketRAM in case of “Low” logic level on TX_EN pin, a new data in PacketRAM during transmission I am not write. Timing intervals between two adjacent packets are high enough (see pictures below).

Could you give me an advice, what is the problem of staying TX_EN pin always “High”? How to achieve possibility to send data packet, for example, 256 bytes as it is mentioned in datasheet (max size of user payload)?


Below I attach detailed steps of initialization of ADF7242:

T_PC_RESET // initial Reset of chip
T_IDLE   // enter to IDLE mode          
T_BRAM_WR // Writing to BBRAM
T_BRAM_RD  // Validating data is written in BBRAM
T_MCR_WR  // Writing to MCR
T_MCR_RD  // Validating data is written in MCR
T_PHY_RDY  // enter to T_PHY_RDY  mode
T_RC_TX // enter to transmitting mode
T_PKT_WR  // Writing to PacketRAM
T_PKT_tx  // The same as RC_TX + pause 20us. Without this delay chip is not send data.

Writing in MCR, on the left – address of register, on the right – its value:

0E      4E //data_rate_high=0x4E; datarate 2000kbps
0F     20 //preamble_num_validate
04     32 //dr0
h05     h06 //dr1
h06     h03 //tx_fd
35     28 //dm_cfg0
89     05 //dm_cfg1
8B      AA //lirf_cfg
9B      1D //tx_m
B4     80 //synt          
B6     37 //agc_max
B7      2A //agc_cfg2
B8     1D //agc_cfg3
B2     h34 //agc_cfg4
BA     h24 //agc_cfg4
BC      7B //agc_cfg6
BF      00 //agc_cfg1
CB     FF //ocl_cfg0
CC      FF //ocl_cfg0
C7      00 //ocl_bw0
C8     00 //ocl_bw1
C9     00 //ocl_bw2
CA     00 //ocl_bw3
CB     FF //ocl_bw4
CC     FF //ocl_bw5
C4     07 //ocl_bw13
D2      1A //afc_ki_kp
D3     19 //afc_range
D4     1E //afc_cfg
D5      1E
D6     1E
D7     00
E0     F0
F3     01

:Writing in BBRAM: 

00     18 //8'h18
0C     31//rc_cfg     
0D     7F //sync_word0 (0x10C)
0E     AA //sync_word1 (0x10D)
0F     10 //sync_word2 (0x10E)        
3E     h04

On picture - an example of successful transmitting data packet (138 bytes): green line - TX_EN, yellow – clock signal of SPI-interface (writing in PacketRam at Fclk = 6 MHz). We can see, that after writing in PacketRam (yellow rectangle) and issuing RC_TX (yellow spike on the right) TX_EN goes to “High” and staying in this state until transmitting is ended. After that it drops to “Low”:


On the pictures below - pictures in larger scale: is more convenient to see the time intervals: