Hi, ADI Team
We implement AD5410 as our solution and recently have occurred a issue that the Iout drop to zero randomly.
Attached is our schematic, we have these design as below:
1. use internal LDO(DVcc)
2. use internal Rset
3. Set Iout range 4mA-20mA
4. SPI CLK=1MHz
this project can work normally at our company when testing
but some site of customer occurred this issue recently.
1. Dropping frequency is fluctuating though out the year. Since last couple of weeks, dropping frequency is very high (almost once in 3 days).
2. when the board is still in fault condition(this means Iout drop to zero), we measeured that the voltage between R3_Sense and Boost is zero, and the Fault pin is still active high, DVcc=4.45V
after we active system reset signal, AD5410 works fine, we measured the voltage between R3_Sense and Boost is 0.692V
Additionally, we have a shield wire and its length is about 5 feet long between the Iout connect to PLC
my question as below:
1. can the inteernal LDO has the capability to supply ADuM1400 , ADuM1200 and pats of AD5410 pull high termination?
2. if the soreware issue, especially clear , Iout should drop to 4mA rather than 0mA, there is no decoupling cap for AVdd, can this defect cause this issue?
3. the pad on the bottom of the chip is for thermal dispation, right? if we didn't connect the pad to AGND, dese the chip will be uncontrollable in some condition except thermal issue?
4. poor layout could cause this issue? I mean poor grounding
Could you help to give us some idea