I'm uncertain after reading the UG. In the 9361 data was passed in 12 bit twos complement. In the 9371 there is no such mention of that, but this seems to be 16 bit now. Is data passed as twos complement still, or as signed int?
In AD9371, ADC gives data as 16 Bit I and Q and this goes into the JESD framer . On Tx , The deframer receives 8B10B encoded data from the deserializer and decodes the data into 16-bit DAC samples. Because the DAC samples are only 14-bit, the AD9371 uses the upper 14-bits of the 16-bit word DAC sample. Data is 16Bit signed integer .
Ok, so you are saying the ADC has 16 bit resolution but DAC only has 14 bit, so the 2 LSB of the I and Q are dropped when transmitting, correct? But it is still 16 bit words being both transmitted and received over the digital interface.
And when you say signed integer, that is Sign-Magnitude, and not 2s complement, correct?
2s complement in hardware or integer (signed integer as variable declaration in code).
I see. So why, if that is the case, is data passed through the FPGA in 32 bit words rather than 16? Is that data left or right padded?
Moving to FPGA subspace.
This question was answered in the following thread: AD9371: Why are DAC channels 32 bit when the data is 14 bit?
Will close this one.
Retrieving data ...