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DDR2 loopback test of ADV8005

Question asked by Kikka on Aug 19, 2016
Latest reply on Aug 26, 2016 by Kikka



I tried the DDR2 loopback test with the following procedure using EVAL-ADV8005-SMZ.


1. power-up the EVAL-ADV8005-SMZ

2. write the loopback script

3. read 0x1AE1(lbk_test_done and lbk_test_result)



loopback script (from How do I get the DDR2 loopback test working on ADV8005 or ADV8003? )

    0x1A, 0x1A5B, 0x42, // ; DDR2 change the SDRAM to be 2Gb

    0x1A, 0x1A5F, 0x00, // ; DDR2 enable full drive strength

    0x1A, 0x1A61, 0x06, // ; DDR2 correct rdy_wr_b advancement

    0x1A, 0x1AA0, 0x13, // ; DDR2 plldll recommended values

    0x1A, 0x1AA1, 0x01, // ; DDR2 plldll power up, pll loop filter bandwidth = 1

    0x1A, 0x1AA2, 0x25, // ; DDR2 pll div 37

    0x1A, 0x1AA3, 0x1D, // ; DDR2 pre pll div ratio

    0x1A, 0x1AA4, 0x81, // ; phase selection for Memory Interface

    0x1A, 0x1AA5, 0x81, // ; phase selection for Memory Interface

    0x1A, 0x1AA7, 0x53, // ; Enable DDR2 loopback test on init

    0x1A, 0x1AA8, 0xB4, // ; DDR2 Power up pads

    0x1A, 0x1AFE, 0x08, // ; Start init and loopback test

    0x1A, 0x1A0B, 0x10, // ; enable pseudo 444 to real 444

    0x1A, 0xE649, 0x40, // ; bypass Secondary VSP

    0x1A, 0x1A9D, 0xFF, // ; Default 0x00, DDR2 clk Drive Strenght

    0x1A, 0x1A9E, 0x55, // ; Default 0x00, DDR2 clk Drive Strenght



But it seems that 0x1AE1 register is 0x03. it means lbk_test_done=1(Loopback test finished) and 

lbk_test_result=1(Errors detected).

Would you please check it and tell me your advice?


Best regards.