Question asked by EricBecker on Aug 18, 2016
Latest reply on Aug 25, 2016 by EricBecker

Hello,

I am performing diagnostic checks on an AD9681 ADC, and I am getting a poor result for my INL. This is a re-post of the last question from another thread that was not answered: Theoretical hits for sine wave input .

The setup is that the ADC is connected to the FPGA, and I have verified that the connection and de-serialization work as expected. I use the FPGA to obtain a hits-per-code histogram from a 10 Hz sine wave using a signal generator (Agilent 33500 B-series). I then compute the DNL based on a simulated sine wave generated in MATLAB that gives me the number of hits I should theoretically receive for each ADC code. Figure 1 below show the theoretical hits in red and the actual hits in blue, which look to be in close agreement. When I compute DNL based on this (shown in figure 2), the result isn't perfect at the lower and higher ends of the code, but I may need to do some finer tuning of where the mid-code is for my setup.

Figure 1: Real hits (blue) vs theoretical hits (red).

Figure 2: DNL based on the histogram in Figure 1.

The main issue is that when I compute the INL based on the DNL, the result I get (shown in figure 3) does not look good.

Figure 3: INL based on the DNL in Figure 2.

My method for performing all of these measurements and calculations follows the document here: http://www.analog.com/library/analogDialogue/archives/39-06/Chapter%205%20Testing%20Converters%20F.pdf ,

where the INL of each code is simply the sum of the DNL values for every code up to that point. I have also tried this with a ramp function (so a constant theoretical number of hits per code), and ended up with the same kind of INL shape, with high negative values by the end.

Is there an additional factor I am not accounting for? Since the INL for both the sine wave and ramp look the same I assume there must be something I am missing, but I have thus far not been able to find it. Any help is greatly appreciated!

cheers,

Eric