AnsweredAssumed Answered

SYSREF configuration on the AD9528

Question asked by EJK on Aug 18, 2016
Latest reply on Aug 23, 2016 by rejeesh

Hi,

I am problems configuring the SYSREF generation on the AD-FMCADC4 board.

 

I have experimented with 2 scenarios:

1.  Internally generated SYSREF, using the following register settings:

0x327 : 0x40

0x328 : 0x01

0x329 : 0x3F

0x400 : 0x14

0x401 : 0x00

0x402 : 0x00

0x403 : 0x91

0x404 : 0x04

 

2.  Externally generated SYSREF, using the following register settings:

0x327 : 0x40

0x328 : 0x01

0x329 : 0x3F

0x400 : 0x14

0x401 : 0x00

0x402 : 0x00

0x403 : 0x11

0x404 : 0x01

 

Since on the FMCADC4 the SYSREF input can only be driven from the carrier board, I've configured my FPGA to generate a square wave with a period of 1 us.

 

When I probe FMC pin D8, I see the same thing for both cases:  a square wave that has a period of either 0.977 us or a period of 1.042 us.   It seems that regardless of how I configure the AD9528, it is internally generating SYSREF, and the source signal is bouncing around.

 

Could someone please tell me what is going on?

 

Thanks.

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