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AD1974 ABCLK and ALRCLK for ADC slave mode

Question asked by ak1000 on Aug 10, 2011
Latest reply on Aug 11, 2011 by AndyR

Hello,

 

If using the AD1974 in slave mode, ie. the ABCLK and ALRCLK are clock inputs do they have to be synchronized to the sample rate?  According to the datasheet these clocks are synchronous to the sample rate and that makes sense when they are outputs, but no explicit conditions are given when they are inputs.  The only requirement I see is that there is a setup and hold time requirement on the ALRCLK in relation to ABCLK when the AD1974 is in slave mode.  My customer plans to drive ABCLK nad ALRCLK with a FPGAor DSP and wanted to know if they have to be synchronized to the sample rate.

 

SERIAL DATA PORTS—DATA FORMAT

The four ADC channels use a common serial bit clock (ABCLK) and a left-right framing clock (ALRCLK) in the serial data port. The clock signals are all synchronous with the sample rate. The normal stereo serial modes are shown in Figure 11.

 

ADC SERIAL PORT

See Figure 13

t

ABH

ABCLK high

Slave mode

10

ns

t

ABL

ABCLK low

Slave mode

10

ns

t

ALS

ALRCLK setup

To ABCLK rising, slave mode

10

ns

t

ALH

ALRCLK hold

From ABCLK rising, slave mode

5

ns


Thanks,

 

Ali

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