Hi, I am using ADRF6620-Evalz board to test performance of ADRF6620's internal PLL LO signal's phase noise and spurious emission performance.
Here is what I did.
-Connect 20MHz PLL reference clock signal to REFIN port of evalz board
-Set desired LO frequency on ADRF6620-EVALZ software.(2000MHz)
-Enable LO_DRV_EN bit in Register 0x01, Bit 7. to check LO signal
-Connect LO out port to spectrum analyzer to see internally generated LO signal's phase noise and spur.
Here is the result I get from this test.
Too many spurs were generated. ( attached CSV file of this measured data)
So I checked Lock_detect signal at MUXOUT pin on EVALZ board(to see if it shows logic high, indicating PLL is locked). There was no signal on this lock_detect pin, which means it probably failed to calibrate PLL frequency.
Is there a way to lock LO frequency and remove spurs?