I'm relatively new to capacitive sensing applications. The AD7147 appears to meet my requirements but I have two areas of ambiguity from the documentation.
After reviewing AN-957 the ACShield plane recommendation is not clear to me on page 2 bullet 4: "The ACSHIELDplane should be at least 1 mm around the sensors and sensor traces". I can see 3 different interpretations (see image below)
- 1mm is the gap from one side of the plane to the sensor/trace
- 1mm is the gap from one side of the plane to the other side of the plane with the sensor/trace in the middle (i.e. plane to trace is .5 mm gap)
- 1mm is the minimum plane width surrounding the sensors/traces, as in the case where sensors or traces are close together
Which of these 3 (or another) is the correction interpretation?
My application requires a maximum 10ms scan time for each sensor. The datasheet Rev E indicates on page 1 "9 ms update rate, all 13 sensor inputs". This corresponds to "Table 10. CDC Conversion Times for Full Power Mode" on page 17, at Decimation = 64. I will only use 8 stages and this is below my max.
If Decimation = 64 is inadequate and I'm forced to increase decimation to 128 @ 8 stages, the conversion time 13.824ms would exceed my maximum acceptable time. I need to be reasonably sure that 64 can provide adequate performance for typical applications.
For those with experience using this product at the minimum decimation setting of 64, what was your experience?
Below and attached are front/back 2-layer test board designs. I very much appreciate any feedback on the design if anything jumps out.